Careers

FPGA Design Engineer (Chandler, AZ) 13705

12+ Month Contract

Pay Rate: Open for the right candidate

US Citizenship Required

FPGA Design Engineers needed to participate in the complete life-cycle development of avionics for launch vehicles and design testing systems. This position involves identifying, investigating, designing, and developing programmable logic solutions using VHSIC Hardware Description Language (VHDL) to address various technical challenges. Testing programmable logic designs in the lab using industry standard tools and equipment to ensure performance and functionality meet design requirements is also required.

This role can be either for a Principal Engineer or Senior Principal Engineer Digital.

Basic Qualifications for Principal Engineer Digital:

• B.S. degree in Electrical Engineering (Computer or Electrical), or related field, and a minimum of 5 years of relevant professional work experience OR
• M.S. degree and a minimum of 3 years of relevant professional work experience in EE/CE, including programmable logic design
• Recent experience with Hardware Description Language (VHDL) and formal verification (preferably OSVVM) for FPGAs, CPLDs, and/or ASICs
• Ability to work in teams and effectively communicate with engineers at different levels
• Capability to translate system performance and operational specifications into programmable logic requirements, design specifications, test specifications, and users' guides
• US Citizenship with the ability to obtain and maintain a Security Clearance

Preferred Qualifications:

• Experience with Electronic Design Automation (EDA) Tools: Mentor Graphics ModelSim/QuestaSim, Radiant (Lattice), Vivado/ISE (Xilinx), Libero (Microsemi)

The ideal candidate will have familiarity with:

• Communication protocols (UART, SPI, I2C, 1-Wire, Ethernet, AXI, APB, SpaceWire)
• Fixed-point math fundamentals
• Static timing analysis and timing closure (setup and hold, slack, skew, etc.)
• Asynchronous clock domain crossing and general metastability mitigation techniques
• Test-bench development, including timing-accurate bus functional models and complete functional coverage
• Working in an Agile project format, team-based environment, including Jira and Git environments
• Formal verification with OSVVM